64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No.
First Version Release
1.0
1. Changed tOH: 2.0 --> 2.5
[tCK = 7 & 7.5 (CL3) Product]
1. Changed Input High/Low Voltage (Page 08)
2. Changed DC characteristics (Page 09)
- IDD2NS: 18mA -> 15mA
- IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA
[Speed 200 / 166 / 143 / 133MHz]
3. Changed Clock High / Low pulse width Time (Page 11)
4. Changed tAC Time (Page11)
5. Changed tRRD Time (Page12)
1. Corrected Revision No.: 2.0 -> 1.1
2. Deleted Remark at Revision History
3. Corrected AC OPERATING CONDITION
- CL 50pF -> 30pF
4. Changed DC OPERATING CONDITION
- VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0
- VIL MIN VSSQ-2.0 -> -0.3
1. Modified note for Super Low Power in ORDERING INFORMATION
1. Corrected PIN ASSIGNMENT A12 to NC
1. Corrected comments for overshoot and undershoot
Nov. 2004
History
Draft Date
Remark
1.1
Dec. 2004
1.2
Dec. 2004
1.3
1.4
1.5
Jan. 2005
Jan. 2005
Feb. 2005
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.5 / Feb. 2005
1
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
DESCRIPTION
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of
1,048,576x16.
HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
•
•
Voltage: VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
54 Pin TSOPII (Lead or Lead Free Package)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
•
Internal four banks operation
•
Burst Read Single Write operation
Programmable CAS Latency; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY57V641620E(L/S)T(P)-5
HY57V641620E(L/S)T(P)-6
HY57V641620E(L/S)T(P)-7
HY57V641620E(L/S)T(P)-H
Clock Frequency
200MHz
166MHz
143MHz
133MHz
4Banks x 1Mbits x16
LVTTL
54 Pin TSOPII
Organization
Interface
Package
Note:
1. HY57V641620ET Series: Normal power, Leaded.
2. HY57V641620ELT Series: Low power, Leaded.
3. HY57V641620EST Series: Super Low power, Leaded.
4. HY57V641620ETP Series: Normal power, Lead Free.
5. HY57V641620ELTP Series: Low power, Lead Free.
6. HY57V641620ESTP Series: Super Low Power, Lead Free
Rev. 1.5 / Feb. 2005
2
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
PIN ASSIGNMENTS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
54 Pin TSOPII
400mil x 875mil
0.8mm pin pitch
Rev. 1.5 / Feb. 2005
3
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
PIN DESCRIPTION
SYMBOL
CLK
TYPE
Clock
DESCRIPTION
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
CKE
CS
BA0, BA1
Clock Enable
Chip Select
Bank Address
A0 ~ A11
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power /
Ground
No Connection
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
Rev. 1.5 / Feb. 2005
4
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh
logic & timer
Internal Row
Counter
CLK
CKE
State Machine
Row Active
1Mx16 BANK 3
Row
Pre
Decoder
1Mx16 BANK 2
1Mx16 BANK 1
1Mx16 BANK 0
DQ0
I/O Buffer & Logic
Sense AMP & I/O Gate
X-Decoder
X-Decoder
X-Decoder
X-Decoder
CS
RAS
CAS
Refresh
Memory
Cell
Array
Column Active
WE
U/LDQM
Column
Pre
Decoder
DQ15
Y-Decoder
Bank Select
Column Add
Counter
A0
A1
Address Buffers
Address
Register
Burst
Counter
A11
BA1
BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line
Control
Rev. 1.5 / Feb. 2005
5
RF/无线
